Metal oxide semiconductor field effect transistor (MOSFET) devices may be broadly categorized according to the relative arrangement of source, gate and drain terminal structures, or the orientations of the source-to-drain channels relative to the surfaces of the semiconductor substrates on which the devices are formed. In a lateral channel MOSFET (lateral MOSFET), a source region and a drain region are arrayed in a lateral direction of a semiconductor substrate. The gate electrode is disposed on the silicon substrate between the source and drain regions. This lateral configuration of source, gate, and drain regions may be suitable for making smaller devices and for device integration. However, this lateral configuration may not be suitable for obtaining high power ratings for the devices because, for instance, the voltage blocking capability (breakdown voltage) of such a device can be proportional to the source-drain separation, and because the drain-to-source current can be inversely proportional to the length.
For power applications, vertical channel or trench gate MOSFETs (vertical MOSFETs) may be preferred. In some vertical channel MOSFET implementations, source, gate and drain regions are arranged in a vertical direction of a semiconductor substrate and/or a semiconductor layer. In such approaches, the source and drain terminals may be placed on opposite sides of a semiconductor substrate, and a gate electrode may be disposed in a groove or trench that is etched in the semiconductor substrate and/or semiconductor layer. This vertical configuration may be more suitable for a power MOSFET device, as the source and drain separation can be reduced. For instance, reduction of the source and drain separation can increase the drain-to-source current rating, reduce drain-to-source resistance RDS(on) while the transistor is on and also can allow for the use of an epitaxial layer for the drain drift region, which may increase the device's voltage blocking capability (e.g., increase the device's breakdown voltage).
In such vertical MOSFET devices, electrical connections can be applied to both sides of the package to provide a source connection and a gate connection (on one side), and a drain connection (on an opposite side). Using such an arrangement can make it difficult to package such transistors, particularly in packaging approaches such as Wafer Level Chip Scale Packaging (WLCSP), where electrical connections are typically available only on one side of a device.
When using WLCSP (or similar techniques) to package transistors, it may be desirable to place all the contacts for the transistor, including a source contact, a drain contact and a gate contact on the same side of the semiconductor substrate. This type of configuration allows for easy connection to circuit board traces using solder balls on a single surface of a substrate (e.g., in WLCSP) that are connected to each of the terminals of a given transistor.
However, implementing vertical MOSFET devices (e.g., power trench MOSFETs) in such a direct-drain (e.g., all electrical contacts on one side) configuration (which, for purposes of this disclosure, may be referred to as a direct-drain trench FET and/or a direct-drain FET) has a number of drawbacks. For instance, the arrangement of a source region, a well (body) region, a gate trench and a drain region in a direct-drain trench FET may result in a parasitic FET being formed, where the parasitic FET may cause undesired leakage from source to drain. Further, as source to drain spacing is reduced in a direct-drain trench FET, source to drain leakage may increase through the well region. In existing implementations, such leakage current can be reduced by increasing spacing between the source region and the drain region of the FET in order to reduce the efficiency of the parasitic MOSFET and/or by using a field plate to block formation of the well region between the source and drain. This increased source to drain spacing undesirably increases RDS(on) of the transistor and, therefore, limits the current rating of the transistor. Furthermore, increasing drain to source spacing results in increases to the size of a semiconductor substrate on which such a direct-drain trench FET is produced, thus increasing manufacturing costs.